Programmable FPGA Server Adapter
FB4XXVG@Z21D TimeSync SmartNIC FPGA Xilinx® based
Quad Port SFP28 10/25 Gigabit Xilinx® TimeSync FPGA Card
The TimeSync SmartNIC FPGA FB4XXVG@Z21D is a high-performance OEM hardware platform intended for hardware acceleration for mobile 4G and 5G Baseband Units or Distributed Units with four SFP28 modules. Example: supports 100MHz carriers Radio Units via 4×10/25G eCPRI/CPRI with SFP28 modules, as well as interfacing to a Grand master via SFP28 at 10/25G.
The design is set to work in ORAN LLS-C1 and C2 with the intention to be utilized with a 4G/5G IP stack interfacing at 3GPP functional split options 8 for CPRI or 7.2x for eCPRI.
The card is based on a Xilinx® Zynq UltraScale+ RFSoC FPGA, which embeds a Processor System (PS) with four 64-bit Application Processing Units (ARM Cortex-A53) and two Real-Time Processing Units (ARM Cortex-R5) along with a powerful Programmable Logic (PL) part (UltraScale+ FPGA), as well as an integrated SD-FEC block.
Key Features
- 5G Fronthaul with FEC offload/in-line acceleration
- IEEE-1588-2019 compliance, Synchronous Ethernet (SyncE)
- SmartNIC with easy customer IP integration, DPDK support
FB4XXVG@Z21D TimeSync SmartNIC FPGA Xilinx® based
Quad Port SFP28 10/25 Gigabit Xilinx® TimeSync FPGA Card
- 5G Fronthaul with FEC offload/in-line acceleration
- IEEE-1588-2019 compliance, Synchronous Ethernet (SyncE)
- SmartNIC with easy customer IP integration, DPDK support
- Xilinx® Zynq UltraScale+ RFSoC FPGA
- 1 x 4GB DDR4 (with ECC) for Programmable Logic (FPGA/PL)
- 1 x 4GB DDR4 (with ECC) for Processing System (CPU/PS)
- 2 x 1Gb QSPI NOR Flash for primary and failsafe image booting
FB4XXVG@Z21D TimeSync SmartNIC FPGA Xilinx® based
Quad Port SFP28 10/25 Gigabit Xilinx® TimeSync FPGA Card
Network Interface |
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IEEE standard |
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Ports |
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Host and Card Interfaces |
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PCI bus |
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Other |
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Antenna Interface |
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SMA |
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Environment |
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Physical |
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Cooling |
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Power |
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FPGA Design Specification |
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ZU21DR Resources |
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TimeSync HW |
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TimeSync SW |
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Onboard Memory |
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SmartNIC |
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DPDK |
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Firmware configuration
The SmartNIC FPGA Design is based on the OpenNIC platform which incorporates an RTL based low latency NIC shell and Linux Kernel driver. The NIC implementation supporting up to four PCIe physical functions (PF), with each up to 256 virtual functions (VFs), and four 10/25Gbps Ethernet ports. The shell is equipped with AXI based data and control interfaces which designed to enhance easy customer IP and user logic integration.
The onboard time synchronization circuit built with a selection of high precision oscillator, onboard GNSS receiver and Microsemi’s miTimePLL timing technology, that offers a robust and field-proven synchronization Solutions for Next-Generation 5G Applications. As for the PTP SW stack you can choose from the carrier grade Microchip PTP stack, or the opensource LinuxPTP stack, both running on the embedded ARM CPUs inside the Zynq FPGA.
There is a selection of 3rd party IPs for L1 offload and inline acceleration performing LDPC and Turbo codes from our partners.
The following table shows the available software configurations for the card:
FPGA FW |
PTP stack |
Host SW |
OpenNIC 4×10/25G | PTP4L | OpenNIC driver, RawCardTool, DPDK, Linux PTP stack |
OpenNIC 4×10/25G | ZLSPTP | OpenNIC driver, RawCardTool, DPDK, Microchip PTP stack |
Look aside LDPC offload | N/A | 3rd party HOST driver, RawCardTool, DPDK, BBDEV |
In-line LDPC acceleration | ZLSPTP | 3rd party IP, Contact for more information |
FB4XXVG@Z21D TimeSync SmartNIC FPGA Xilinx® based
Quad Port SFP28 10/25 Gigabit Xilinx® TimeSync FPGA Card
Hardware configuration
The card can be configured with different standard or high-quality oscillators and can be ordered with or without an onboard GNSS receiver, as well as with an additional SyncBracket.
Please see the table below on the available hardware configurations:
P/N |
Description |
FB4XXVG@Z21D-2-LGP0 | SMA set for GPS, Standard Oscillator, No secondary SyncBracket |
FB4XXVG@Z21D-2-LPP0 | SMA set for PPS, Standard Oscillator, No secondary SyncBracket |
FB4XXVG@Z21D-2-HGP0 | SMA set for GPS, HQ Oscillator, No secondary SyncBracket |
FB4XXVG@Z21D-2-HPP0 | SMA set for PPS, HQ Oscillator, No secondary SyncBracket |
FB4XXVG@Z21D-2-LGP1 | SMA set for GPS, Standard Oscillator, With secondary SyncBracket |
FB4XXVG@Z21D-2-LPP1 | SMA set for PPS, Standard Oscillator, With secondary SyncBracket |
FB4XXVG@Z21D-2-HGP1 | SMA set for GPS, HQ Oscillator, With secondary SyncBracket |
FB4XXVG@Z21D-2-HPP1 | SMA set for PPS, HQ Oscillator, With secondary SyncBracket |