PE310G4DBI9-T 10G NIC

Quad port Copper 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

PE310G4DBI9-T 10G NIC

Quad port Copper 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

Content Aware Director:

• Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass)
• Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules that specify which packets are copied to the host system (TAP)
• Provides intelligent packet filtering / drop capability where rules specify which packets are directed to the host or dropped
• Provides redirection rules that can be defined using source IP/ destination IP / Source Port / Destination Port / VLAN tuples
• Redirection and packet filtering / drop are performed by the hardware itself in wire speed and do not require any software and CPU host system power processing
• Intelligent redirect mechanism is controllable via software
• Intelligent routing mechanism is controllable via software

Bypass / Disconnect:

• Bypass / Disconnect Ethernet ports on Power Fail, System Hangs or Software Application Hangs
• Software programmable Bypass, Disconnect or Normal Mode
• On Board Watch Dog Timer (WDT) Controller
• Software programmable time out interval
• Software Programmable WDT Enable / Disable counter
• Software programmable Bypass Capability Enable / Disable
• Software Programmable Disconnect Capability Enable / Disable
• Software Programmable mode (Bypass, Normal or Disconnect mode) at Power up
• Software Programmable mode (Bypass, Normal mode) at Power off
• Emulates standard NIC

Copper 10Gigabit Ethernet 10GBase-T :

• Integrated 10 Gigabit Copper PHY supports 10GBASE-T, 1000 BASE- T and 100BASE- TX
• Triple speed 10Gbps (10GBase-T), 1000Mbps (1000Base-T) and 100 Mbps (100Base-T)
• RJ-45 connector supports CAT 6A, CAT7 cable

Common Key features
Host Interface:

• PCI Express X8 lane
• Support PCI Express Base Specification Revision 3.0, 8GT/s, 5GT/s or 2.5GT/s

Intel FM4410 Features:

• Cut-true latency 300nS
• On chip 2Mbyte shared memory
• Traffic Classes: 8
• MAC table Size: 16K
• ACL Rule 16K
• IPv4 / IPV6 Routers 16K / 4K

Intel 82599 Features:

• IPV6 Supports for IP/ TCP and IP/UDP Receive Checksum offload
• Fragmented UDP checksum offload for Packet Reassembly
• Receive Side Scaling minimize CPU utilization across multiple processor systems
• Support for 16 virtual machine Device Queues (VMDq) per port
• Advanced memory architecture reduces latency
• Minimized device I/O interrupts using MSI and MSI-X
• Offload of TCP / IP / UDP checksum calculation and TCP segmentation
• Large on chip receive packet buffer 520 KB / per port
• Large on chip transmit packet buffer 160KB / per port

LAN Features:

• Jumbo Frame (up to 9.5KB).
• LEDs indicator for link/Activity

PE310G4DBI9-T 10G NIC

Quad port Copper 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

Functional Description

Silicom’s 10 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass)

Figure 1: Content Aware Bypass Functional Block Diagram

Figure 1 illustrates functional block diagram of content aware Bypass:

Packets received in port A and meet rule are directed to port B, other packets are directed to port C (Bypass).

Packets received in port C and meet rule are directed to port D, other packets are directed to port A (Bypass).

Director - Content Aware TAP

Silicom’s 10 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules specify which packets are copied to the host system (TAP).

Figure 2: Content Aware TAP Functional Block Diagram

Figure 2 illustrates functional block diagram of content aware TAP:

Packets received in port A and meet rule are directed to ports B and C (TAP), other packets are directed to port C (Bypass).

Packets received in port C and meet rule are directed to ports D and A (TAP), other packets are directed to port A (Bypass).

Director - Content Filtering NIC

Silicom’s 10 Gigabit Ethernet content aware provides intelligent packet redirection capability where rules specify which packets are directed to the host or dropped.

Figure 3: Content Aware Filtering NIC Functional Block Diagram

Figure 3 illustrates functional block diagram of content aware TAP:

Packets received in port A and meet rule, direct to port B. Packets received in port A and do not meet rule are dropped.

Packets received in port C and meet rule, direct to port D. Packets received in port C and do not meet rule are Dropt.

Load Balancing

Silicom’s 10 Gigabit Ethernet content aware director provides a load balancing of the traffic coming from the 4 x 10G external ports (0,2,4 and 6). The traffic is balanced, based on a defined hash configuration (5 tuple or other), to the 4x 10G internal interfaces ( 1,3,5 and 7)that are going to the host.

Figure 4: Load Balancing Functional Block Diagram

Figure 4 illustrates functional block diagram of Load Balancing:

Packets received in the 4 x 10G external ports (0,2,4 and 6) to be balanced based on a defined hash configuration (5 tuple or other), to the 4x 10G internal interfaces (1,3,5and 7) that are going to the host. If there is external port that is heavily loaded the traffic will go into the 4 internal interfaces with balanced load. An ISL tag is added to all incoming packets, it enables the host to know the source port, packets that are sent back from the host are stride from the ISL tag.

Tagged In-Line rule aware mode

Silicom’s 10 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other ports (Bypass) but at the same time it will get these bypassed trfic into the host with a ISL tag marking that these packets are bypassed, per the rules that the host will issue to the Silicom’s 10 Gigabit Ethernet content aware director.

Figure 5: Tagged In-Line rule aware mode Block Diagram

Figure 5 illustrates functional block diagram of Tagged In-Line rule aware mode:

Port Group (0, 1), (2, 3), (4, 5), (6, 7) configured as VLAN groups.

Packets received in the 4 x 10G external ports (0,2,4 and 6) and meet and are directed to the other ports of the Vlan group with ISL tag that notify that match found. The original packet is sent to the “Output Port of Switch” in the rule matched policy

Packets received in the 4 x 10G external ports (0,2,4 and 6) and do not meet the rule are directed to the other ports of the Vlan group taged with ISL tag that notify that no-match found.

Director: Rules Classification and capabilities

Director Capabilities

• The Redirector supports the following capabilities:
• Maximum total number of rules is 16K
• Each of the 16K rules can be defined to any port the on board multi-layer switch
• Each rule refers to incoming packet
• Rules are executed per order. First rule that matches will be executed
• Rules can be added and removed on the fly
• Each rule can include one or more classification fields. A rule match will be when all fields defined are match
• Each field can have a bit masking to check part of the classification field
• Per port statistics can be read, like packets count, errors, VLAN, and more
• Rules and action are done in wire speed at any packet size

Rules classification fields

Rules classification is done based on the first 128 bytes of the packets. The following list provides rules classification fields

• MAC address, source & destination
• IPv4 – source & destination IP
• IPv6 – source & destination IP
• L4 Port – source & destination port
• Ethernet Protocol – ethertype
• IP Protocol num
• VLAN ID tagging
• User defined fields
• DSCP – match the different services code point – the six most significant bits of the Type of Service octet (IPv4) or Traffic Class octet (IPv6).*
• IPv6 Flow Label*
• IP length*
• ISL Frame Type*
• ISL USER*
• Source & destination port range*
• VLAN priority*
• VLAN tag type*
• TCP flags*
• TOS – match Type of Service octet (IPv4) or Traffic Class octet (IPv6)*
• TTL field in a IPv4 header or Hop Limit in a IPv6 header*

*Future SW supports

Execution per rule

The following Executions per rule are supported:

• Drop – when a rule matches the packet will be dropped
• Redirect – when a rule matches redirect the packet to the defined destination port
• Mirror – when a rule matches copy packet also to a defined destination port

Director Advanced Features:

• Port trunking between the different Intel 10G ports to the Fulcrum 10G ports connected to it for load balancing between the different Intel ports
• Port trunking between the different External Fulcrum port to the external switch connected to it for load balancing between the different external ports
• Session balancing with L3/L4 hashing or other mechanism
• ISL (Inter Switch Link) Tagging per port can be added to the packets per configuration
• ISL Tagging can be removed and can be forward to specific port per the ISL index
• Quality of Service support with the following features:
• Priority levels: 16 internal "switch" priorities, 8 or 16 VLAN priorities (optional use of CFI bit as an extra VLAN priority bit)
• Arbitrary mapping of ingress VLAN priority to an internal VLAN priority
• Arbitrary mapping of an internal VLAN priority to egress VLAN priority
• Arbitrary mapping of internal VLAN priority to switch priority
• Arbitrary mapping of DSCP to switch priority, configurable priority source selection
• Scheduler: 8 traffic classes, arbitrary mapping of switch priorities to traffic class, deficit weighted round-robin or strict priority
• Notification: Two congestion notifications can be supported
• Virtual output queue congestion notification (VCN) and Intel proprietary backward congestion notification (FCN)
• Open Flow support (consistent with OpenFlow protocol standard)
• sFlow support
• User defined Packet transmission with two optional modes: 1. Simple mode - transmit on specific port. 2. Switched mode - where switch determines destination port/ports, or with specific information such as
• whether or not egress processing rules should be applied
• Storm Control Management - Switch can support a variety storm controller. Each storm controller can be programmable to define rat, condition (like unicast ICMP frames whose TTL is at most 1), frame type (can be
• OR’ed), ingress & egress port ports. Actions: do nothing, drops frames to port (according to filter)

PE310G4DBI9-T 10G NIC

Quad port Copper 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

-SD: Side Driver

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