4G 5G Products
Silicom Palma DU IX4200
DU IX4200 – Ice-Lake-SP ( ICX-SP)
Maximize Performance and Efficiency with the Palma B Distributed Unit Platform
Designed for Edge computing services with a focus on 4G/5G DUs (Distributed Units), the Palma B Distributed Unit platform features an onboard front panel IO for RU (Radio Unit) connectivity, along with Silicom Time Sync (STS) Technology, 5G ACC100 L1 Acceleration, and Remote Management capabilities.
Palma B Distributed Unit: Designed for 4G/5G DUs with Silicom Time Sync and 5G ACC100 L1 Acceleration
Palma B Distributed Unit interfaces are built with a PTP (1588) and SyncE for Time Synchronization, along with 8x10G and 4x25G. This design also offers space for hosting multiple eASIC / FPGA cards for service acceleration in both wireline and wireless deployments.
This design also offers space for hosting multiple eASIC / FPGA cards for service acceleration in both wireline and wireless deployments.
Silicom Palma DU IX4200
DU IX4200 – Ice-Lake-SP ( ICX-SP)
Palma’s special features include:
- PTP (1588) hardware based physical layer TimeStamper and SyncE
- On board ACC100 HW FEC accelerator
- Based on Microchip/ Zarlink Servo
- DU-optimized: features TimeSync and FEC Accelerator on main board Simplest and most reliable design
- Thermally optimized solution for E-Temp
- GNSS on board
- Timing ports: 1PPS out, 1PPS in, 10MHz out, 10MHz in
Silicom Palma DU IX4200
DU IX4200 – Ice-Lake-SP ( ICX-SP)
General Technical Specifications |
|
| CPU: | Intel Xeon Ice Lake (ICX-SP), Socket P+, 4189 pin, Single Socket 32C/2.2GHz/185W/XCC Intel Code 6338N 16C/2.4GHz/135W/HCC Intel Code 4314 |
| Chipset: | LBG-R, C621A |
| Memory: | Supports up to 16 DIMMs/ DDR4 with ECC, 8 DDR channel controllers DDR Maximum Speed 3200 MT/s |
| Storage: | 120GB M.2 NVME |
| PCI#1 – 6: | Total BW PCIe x64G4, slots 2&3 (x16G4) available for add in card |
| BIOS: | UEFI, Secure Boot |
| BIOS/ BMC: | SPI, Dual redundant images for both x86 and for the BMC |
| Operating System: | Linux/ CentOS |
| Host Mgmt.: | (1) 1GbE RJ45 Management via BMC and in-line management via CLV. |
| USB 3.0: | 2xFront, 2x Internal Vertical |
| Serial Console: | RJ45 connector using RS232 signaling direct connection to BMC, via Mux / pass through the x86 |
| BMC: | AST2620 |
| TPM: | TPM 2.0 |
| ROT: | Support, CPLD connected to both SPI images |
| Power Supply: | Dual redundant DC -48V hot swappable power supply 800W |
| Power Supply voltage rate: | (-36v) – (-75v) DC |
| Form Factor: | • 2U rackmount Form Factor EIA 19”, • Depth: 389/385mm, including mountings/ without mounting ears |
| Weight: | 16kg (564oz) |
| Cooling: | 5 FANs |
| Sensors/Monitors: | Thermal protection Critical Error Detection Voltage monitors Current protection |
| Operating Temperature: | 0°C – 40°C (32°F – 104°F) |
| Storage: | -40°C – 65°C (-40°F–149°F) |
| Operating Altitude | 10,000 ft (3,048 m) |
| Certificates: | EMC: EN55032: 2012 + AC (13) FCC 47 CFR part 15 subpart B EN 61000-3-2: 2014 EN 61000-3-3: 2013 EN 55024: 2010 Safety: CB Scheme 62368-1 CB Scheme 60950-1 CE 62368-1 CE 60950-1 ROHS |
SKU1 Features: |
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| Time Sync SKU1 (On board) | Different in number of ports: Single slot, x8 8Ports, 8x10G, 2xQSFP+ QSFP+: 10GBase-SR, 10GBase-LR |
| TimeSync SMA: | x5 SMAs: 1PPS Out (default) or 1PPS In – configurable 10MHz Out (default) or 10MHz In or 1PPS Out – configurable 1PPS Out 10MHz Out GNSS antenna In |
| Profile: IEEE-1588 ( 2008) ( Annex-J.3 Delay Request-Respond Default Profile | Ordinary Clock – Server Ordinary Clock- Client ( including slave only OC) Boundary Clock |
| Profile: IEEE-1588 ( 2008) ( Annex-J.4 Peer-to-Peer | Ordinary Clock – Server Ordinary Clock- Client ( including slave only OC) Boundary Clock |
| Profile: ITU-T G.8265.1 Telecom Profile for Frequency Synchronization | Telecom Grandmaster Telecom Slave |
| Profile: ITU-T G.8275.1 PTP Telecom Profile for Phase with Full timing Support | Telecom Grandmaster ( T-GM) Telecom Boundary Clock ( T-BC) Telecom Time Slave Clock ( T-TSC) |
| Profile: ITU-T G.8275.2 PTP Telecom Profile for Phase with Partial timing Support | Ordinary Clock Boundary Clock Transparent Clock (peer-delay-message exchange) |
| References Selection: | Default BMCA (Best Master Clock Algorithm) Alternate BMCA based on ITU G.781 – Synchronization layer functions for frequency synchronization based on the physical layer |
| On board FEC Accelerator | Silicom PML 5G/4G FEC HW accelerator x16G3 |
SKU2 Features: |
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| Time Sync SKU2: (On board) |
Silicom TimeSync SKU2, 12 ports |
| Network Ports: | 12Ports, 2xQSFP+, 1xQSFP28 QSFP+: 10GBase-SR, 10GBase-LR QSFP28: 25/10GBase-SR, 25/10GBase-LR |
| On board FEC Accelerator | Silicom PML 5G/4G FEC HW accelerator x16G3, same as SKU1 |
Silicom Palma DU IX4200
DU IX4200 – Ice-Lake-SP ( ICX-SP)
P/N |
Description |
RMN |
RTN |
Notes: |
| 90500-0169-G00 | DU, Palma, 2U,19″,32C/2.2GHz, DDR4/128GB/ECC,2xPSU,SKU2 |
IX4200 | IX4200.01 | Includes: 2xDC power cable 1x Ground earth cable, SKU2, 12 ports TimeSync |
| 90500-0169-G02 | DU, Palma, 2U,19″,16C/2.4GHz, DDR4/120GB/ECC,1xPSU,SKU2 |
IX4200 | IX4200.02 | Includes: 1xDC power cable 1x Ground earth cable, SKU2, 12 ports TimeSync |
| 90500-0169-E03 | DU, Palma, 2U,19″,32C/2.2GHz, DDR4/120GB/ECC,1xPSU,SKU2 |
IX4200 | Includes: 1xDC power cable 1x Ground earth cable, SKU2, 12 ports TimeSync |
|
| 90500-0169-E04 | DU, Palma, 2U,19″,16C/2.4GHz, DDR4/120GB/ECC,1xPSU,SKU2 |
IX4200 | Includes: 1xDC power cable 1x Ground earth cable, SKU2, 12 ports TimeSync |
|
| 90500-0169-E05 | DU, Palma, 2U,19″,32C/2.2GHz, DDR4/120GB/ECC,1xPSU,STS2 NIC |
IX4200 | Includes: 1xDC power cable 1x Ground earth cable, STS2 NIC 8 ports TimeSync at PCIe slot #2 |
|
| 90500-0169-E06 | DU, Palma, 2U,19″,16C/2.4GHz, DDR4/120GB/ECC,1xPSU,STS2 NIC |
IX4200 | Includes: 1xDC power cable 1x Ground earth cable, STS2 NIC 8 ports TimeSync at PCIe slot #2 |
|
| 90500-0169-E07 | DU, Palma, 2U,19″,32C/2.2GHz, DDR4/120GB/ECC,2xPSU,STS2 NIC |
IX4200 | Includes: 2xDC power cable 1x Ground earth cable, STS2 NIC 8 ports TimeSync at PCIe slot #2 |
