PacketMover FPGA Acceleration


packetmover silicom fpga-600pxSilicom’s PacketMover is an FPGA framework designed to simplify development and integration of the high-performance / high-flexibility applications and pure-compute tasks that are impossible to create without the use of FPGA, such as heavy computational offload functions, acceleration and networking applications up to 100GE. Typical tasks include compression/de-compression, encryption / decryption, data slicing and Deep Packet Inspection (RegEx). PacketMover’s design makes it applicable for both inline and monitoring solutions.

For satellite communications and automotive use cases, the FPGA card functions as a high-performance bridge between a continuous stream of video data, control data and host computer memory. The pain point in all cases is the poor performance of systems that use software and standard NICs (PCIe DMA or similar), whose header overhead is a huge burden for the software.

Silicom solves this problem by inserting smart algorithms into the FPGA and then encapsulating them using the Silicoms Packet Mover platform.


Other functions like CODEC compression/decompression and access control-based security are also part of these solutions, all nicely encapsulated in the Packet Mover within the FPGA. Due to these acceleration processes carried out within the FPGA, users are able to achieve 100G line-rate performance in their systems. The use of Packet Mover minimizes the development time required for customizations for this type of solution, reducing the development effort by 10 – 15% compared with the use of standard FPGA tools.

By bridging the gap between high-performance applications and supporting hardware, Silicom’s world-class PacketMover platform and FPGA accelerator boards bring reconfigurable computing within the grasp of both system designers and integrators. PacketMover provides an abstraction of the hardware to facilitate the development of custom applications in FPGA.

The PacketMover framework itself consumes only a small fraction of available FPGA resources, leaving the vast majority free for utilization by the Custom Packet Processor. PacketMover serves as an ideal “sandbox” for offload functions or custom applications, and, because it uses standardized interfaces, ensures an easy fit for both custom and standard IP blocks.

The PacketMover framework autonomously manages a variety of complex interfaces, eliminating the need to deal directly with complex network and PCIe hardware. It can provide packets either to the Custom Packet Processer or directly to host-side applications. The PCIe interface is managed by a multichannel DMA system, providing flexible arbitration of multiple channels that can be split among different host-side interfaces, including standard NIC, DPDK and API-controlled buffers on the host, as well as 3rd-party PCIe devices (e.g. GPUs) to keep the host CPU free for tasks unrelated to offloading.


With DPDK support, many industry-standard storage and analysis applications can connect directly to high-performance applications built within the FPGA Custom Packet Processor. The built-in standard NIC function allows the FPGA card to double as a standard network interface for applications or platform traffic, in parallel or in conjunction with custom FPGA-based applications. Using the included API, access to DMA buffers can be achieved with minimal impact on host CPU resources, thereby enabling optimal performance.

The framework’s Frame Forwarder features accurate timestamping while managing the solution’s Rx and Tx. To ensure the optimal application of performance resources, PacketMover offers an Access Control List function that allows data to be sent directly toward the Custom Packet Processor or to bypass it, sending data directly to the host or to a 3rd-party PCIe device.

Controlling applications in PacketMover is very flexible. Direct communication is allowed through custom functions/applications or through configuration and register access.
In addition, the framework provides accurate traffic and rule-match statistics, both for ports and for ACL.


PacketMover FPGA Acceleration enterprise networking magazine

PacketMover FPGA Acceleration Published on enterprise networking magazine