Products

Capture Server Adapters

PE3100G2F2TSTC4

Dual Port 100 Gigabit Ethernet (CFP4) PCI Express Time Stamp Server Adapter Based on Tile Gx72

PE3100G2F2TSTC4 100G Time stamp card

The Silicom’s 100 Gigabit Ethernet PCI Express is third generation of Time Stamp server adapter based on Silicom F2100 – Xilinx Virtex Ultrascale FPGA Time Stamp Engine and Tilera Gx8072.

The Silicom’s 100 Gigabit Ethernet PCI Express Time Stamping server adapter unique architecture leverages capabilities of a Silicom F2100 4nS resolution hardware time stamp engine and the Tilera programmability flexibility of Tilera 72 Tile cores.

PE3100G2F2TSTC4

Dual Port 100 Gigabit Ethernet (CFP4) PCI Express Time Stamp Server Adapter Based on Tile Gx72

Key Features:

  • On board hardware time stamp engine insertion for of every received packet
  • On board precision oscillator OCXO 25MHz / 0.1PPM
  • 4nS time stamp resolution
  • Based on a Tile-Gx8072 processor, optimized to intelligent networking applications
  • Based on third generation of Silicom hardware Time Stamp Engine F2100
  • Seventy-two Tile core operating at 1000MHz
  • Two level of DDR for packet buffers
  • C/C++ programmable
  • 64 bit time Stamp
  • UTC format via synchronization to host OS: GPS or PTP1588v2
  • RJ451 connector for external 1PPS clock source
  • PCI Express X16 lanes Gen3

CFP4 100Gigabit Ethernet:

  • -SR4: Fiber 100 Gigabit Ethernet 100GBASE-SR4:
  • 100BASE-SR4 with 100Gigabit 850nM Small form Factor Pluggable (CFP4)
  • -LR4: Fiber 100 Gigabit Ethernet 100GBASE-LR4:
  • 100BASE-LR4 with 100Gigabit 13100nM Small form Factor Pluggable (CFP4)
  • -SR10: Fiber 100 Gigabit Ethernet 100GBASE-SR10:
  • 100BASE-SR10 with 100Gigabit 850nM Small form Factor Pluggable (CFP4)

1Using Silicom RJ45 to SMA Cable (P/N: MCB#RJ45-MCX-183CM)

block%20diagram time stamping 100g

Building blocks

  • TILE-Gx8072 multi-core processor
  • Xilinx FPGA: XCVU095 with integrated Dual 100 MAC/ PHY
  • 8GByte memory – level one packet buffer data – for FPGA – DDR4 Standard 16-bit wide device – arranged in 4 banks, 2 banks per each 100GE port. On top of the data packet, each bank will include ECC DDR4. Total DDR4 connected to the FPGA 16
  • 8GByte DDR3 memory – level two packet buffer data for TILE-Gx8072 (four interfaces of 2GByte each):8GByte, DDR3 Standard 16-bit wide device – 4Gbit x4 (per bank x4: total 2GByte per bank, total on board (probably memory down) connected to Tilera 8GByte. On top of data, each bank will include ECC. Total DDR3 connected to Tilera 20 DDR3 devices
  • PLX 48-Lane Gen3 switch. Appears that the PEX 8747-CA80FBC G device comes in a 19mm x 21mm package
  • 1588 RJ45 Ethernet port, driven through PLX from x86 host
  • Dual SMA Connectors and level-shifters for 1PPS precision time stamping. One port is the input and the 2nd is for re-driving the signal to another card
  • On board OCXO oscillator

Device Functionality

The 100G Time stamp server adapter captures network traffic. The adapter taps the two directions of a single 100Gbps Ethernet link, split the traffic into flows and then deliver ordered data to the x86 via packet queues over PCI E. An external tap will be used to pass the TX and RX data to this card on the two independent 100G Ethernet ports.

The capture operation is simplex, so data will flow on the RX side of each link. Since the PCI E interface to the host is x16 Gen3 PCI E, this allows a peak of approximately 100Gbps aggregate to the host for medium-to-large PCI transactions. The adapter includes two level of packet buffering provided attached to the FPGA, and the TILE-Gx8072 processor.

The primary functions of the card are as follows:

  • Capture of up to 100Gbps of data from the two optical Ethernet ports
  • Apply precision timestamps to each packet as it arrives to the FPGA. Target is ~4ns resolution to 1PPS clock reference provided on the SMA connector (This is fully FPGA functionality)
  • Apply a sequence ID and port origin (port 0 or 1) to each packet
  • The TILE-Gx72 processor will inspect the packet headers (mPIPE) to classify traffic into programmable flow buckets. These buckets can then be mapped to PCIe SR-IOV queues to individual processors and threads on the x86 host
  • Within each queue to the host x86, the packets will be delivered in sequence order
  • Optionally, certain flows or exception packets may be filtered and dropped at the Gx72, based on configuration provided by the control plane

PE3100G2F2TSTC4

Dual Port 100 Gigabit Ethernet (CFP4) PCI Express Time Stamp Server Adapter Based on Tile Gx72

– SR4: Fiber 100GBASE-SR4 Ethernet Technical Specifications

-SR4 IEEE Standard / Network topology Fiber 100Gigabit Ethernet, 100GBASE-SR4 (850nM LAN PHY)
100GBase-SR4
Cables and Operating distance Up to:
100m

– LR4: Fiber 100GBASE-LR4 Ethernet Technical Specifications

-LR4 IEEE Standard / Network topology: Fiber 100Gigabit Ethernet, 100GBASE-LR (13100nM LAN PHY)
100GBase-LR4
Cables and Operating distance Up to:
10km

– SR10: Fiber 100GBASE-SR4 Ethernet Technical Specifications

-SR4 IEEE Standard / Network topology Fiber 100Gigabit Ethernet, 100GBASE-SR10 (850nM LAN PHY)

Operating Systems Support

Operating system support: Linux

General Technical Specifications

Interface Standard: PCI-Express Base Specification Revision 3.0 (8GT/s)
Board Size: Standard height long (312 x111.5 mm, 12.283 x 4.376 Inch)
PCI Express Card Type: X16 Lane
PCI Express Voltage +12V +- 8%
PCI Connector: X16 Lane
Controller: Silicom F2100
Tilera Gx8072 1000MHz
Holder: Metal Bracket
Weight: 900g(31.75oz)
Power Consumption:
(without transceivers)
160W
Power Consumption –SR4: 167W
Power Consumption –LR4: 170W
Operating Humidity: 0%–90%, non-condensing
Operating Temperature: 0°C – 50°C , Air flow requirement 400LFM
Storage: -40°C–65°C (-40°F–149°F)
EMC Certifications: FCC Part 15, Subpart B Class A
Conducted Emissions
Radiated Emissions
CE EN 55022: 1998 Class A Amendments A1: 2000; A2: 2003
Conducted Emissions
Radiated Emissions
CE EN 55024: 1998 Amendments A1: 2000; A2: 2003
Immunity for ITE Amendment A1: 2001
CE EN 610000-3-2 2000, Class A
Harmonic Current Emissions
CE EN 610000 3-3 1995, Amendement A1: 2001
Voltage Fluctuations and Flicker
CE IEC 61000-4-2: 1995
ESD Air Discharge 8kV. Contact Discharge 4kV.
CE IEC 61000-4-3:1995
Radiated Immunity (80-10000Mhz), 3V/m 80% A.M. by 1kHz
CE IEC 61000-4-4:1995
EFT/B: Immunity to electrical fast transients 1kV Power
Leads, 0.5Kv Signals Leads
CE IEC 61000-4-5:1995
Immunity to conductive surges COM Mode; 2kV,
Dif. Mode 1kV
CE IEC 61000-4-6:1996
Conducted immunity (0.15-80 MHz) 3VRMS 80% A.M.
By 1kHz
CE IEC 61000-4-11:1994
Voltage Dips and Short Interruptions
V reduc >95%, 30% >95% Duration 0.5per, 25per, 250per

LEDs

LEDs: Link/ ACT per port
LEDs location: LED is located on the metal bracket and connected to PCB by connector via short twisted pair cable
Connectors: (2) CFP4 cage
(2) SMA RA ( Time Stamp)
(1) RJ45
(1) Micro USB AB

PE3100G2F2TSTC4

Dual Port 100 Gigabit Ethernet (CFP4) PCI Express Time Stamp Server Adapter Based on Tile Gx72

P/N

Description

Notes

PE3100G2F2TSTC4 Dual Port 100 Gigabit Ethernet (CFP4) PCI Express Time Stamp Server Adapter base on Tile Gx72 Tile Gx72 w/ Silicom Time Stamp Engine, x16G3, standard height, long with CFP4 cage
PE3100G2F2TSTC4-SR4¹ Dual Port 100 Gigabit Ethernet Fiber (SR4) PCI Express Time Stamp Server Adapter base on Tile Gx72 Tile Gx72 w/ Silicom Time Stamp Engine, x16G3, standard height, long supports (SR4) 100GBase-SR4
PE3100G2F2TSTC4-LR4¹ Dual Port 100 Gigabit Ethernet Fiber (SR4) PCI Express Time Stamp Server Adapter base on Tile Gx72 Tile Gx72 w/ Silicom Time Stamp Engine, x16G3, standard height, long supports (LR4) 100GBase-LR4
PE3100G2F2TSTC4-SR10¹ Dual Port 100 Gigabit Ethernet Fiber (SR100) PCI Express Time Stamp Server Adapter base on Tile Gx72 Tile Gx72 w/ Silicom Time Stamp Engine, x16G3, standard height, long supports (SR100) 100GBase-SR100

 

Order information:

*Advanced / SW features are based Tilera Gx8072 NPUs

1 According Transceiver availability
1V5