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PE10G2DBI

Dual port Fiber 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

This product has been discontinuedEOL Notification

Silicom’s 10 Gigabit Ethernet PCI Express content aware director Bypass server adapters is designed for servers and high-end appliances.

The Silicom content aware director server adapter is designed with an on board smart routing architecture that enables packets to be redirected or dropped based on defined rules. The Silicom’s 10 Gigabit Ethernet content aware packet director reduces host system process since only packets that are defined to be targeted to the host systems are routed to the host; other packets can be routed to the other port or can be dropped by the content aware hardware routing architecture.

The Silicom’s 10 Gigabit Ethernet content aware packet director is targeted to network applications that needs to process, monitor or bypass packets based on defined rules. The adapter supports three main modes of operation: Content Aware Bypass, Content Aware TAP and content Aware filtering NIC.

Content Aware Bypass

Silicom’s 10 Gigabit Ethernet content aware director provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass).

Content Aware TAP

Silicom’s 10 Gigabit Ethernet content director provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules specify which packets are copied to the host system (TAP).

Content Aware rules Filtering NIC

Silicom’s 10 Gigabit Ethernet content aware provides intelligent packet redirection capability where rules specify which packets are directed to the host or dropped.

The Silicom 10 Gigabit Ethernet PCI Express content director server adapter is based on Intel 82598 Ethernet controller and a L3 switch router.

The Silicom’s 10 Gigabit Ethernet PCI Express adapter is based on standard L2 driver and with the content director engine reduces CPU host system processing. The Silicom 10 Gigabit Ethernet PCI Express content aware server adapter offers simple integration into any PCI Express X8 to 10Gigabit Network.

Silicom’s 10 Gigabit Ethernet PCI Express content aware supports L1 Bypass. The adapter can Bypass its Ethernet ports on a host system failure, power off, or upon software request. In Bypass mode, the connections of the Ethernet network ports are disconnected from the interfaces and switched over to the other port to create a crossed connection loop-back between the Ethernet ports.

Hence, in bypass mode all packets received from one port are transmitted to other port and vice versa. This feature enables to bypass a failed system and provides maximum up time for the network.

PE10G2DBI

Dual port Fiber 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

Content Aware Director:

  • Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass)
  • Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules that specify which packets are copied to the host system ( TAP)
  • Provides intelligent packet filtering / drop capability where rules specify which packets are directed to the host or dropped
  • Provides redirection rules that can be defined using source IP/ destination IP / Source Port / Destination Port / VLAN tuples
  • Redirection and packet filtering / drop are performed by the hardware itself in wire speed and do not require any software and CPU host system power processing
  • Intelligent redirect mechanism is controllable via software
  • Intelligent routing mechanism is controllable via software

Bypass / Disconnect:

  • Bypass / Disconnect Ethernet ports on Power Fail, System Hangs or Software Application Hangs
  • Software programmable Bypass, Disconnect or Normal Mode
  • On Board Watch Dog Timer (WDT) Controller
  • Software programmable time out interval
  • Software Programmable WDT Enable / Disable counter
  • Software programmable Bypass Capability Enable / Disable
  • Software Programmable Disconnect Capability Enable / Disable
  • Software Programmable mode (Bypass, Normal or Disconnect mode) at Power up
  • Software Programmable mode (Bypass, Normal mode) at Power off
  • Emulates standard NIC

Fiber 10Gigabit Ethernet 10GBase-SR:

  • Short Range Fiber 10Gigabit Ethernet channels support 10GBase-SR
  • LC connectors

Fiber 10Gigabit Ethernet 10GBase-LR:

  • Long Range Fiber 10Gigabit Ethernet channels support 10GBase-LR
  • LC connectors

Common Key features:
Host Interface:

  • PCI Express X8 lane
  • Support PCI Express Base Specification Revision 2.0

Performance Features:

  • IPV6 Supports for IP/ TCP and IP/UDP Receive Checksum offload
  • Fragmented UDP checksum offload for Packet Reassembly
  • Receive Side Scaling minimize CPU utilization across multiple processor systems
  • Support for 16 virtual machine Device Queues ( VMDq) per port
  • Support Direct Cache Access ( DCA)
  • Advanced memory architecture reduces latency
  • Minimized device I/O interrupts using MSI and MSI-X
  • Offload of TCP / IP / UDP checksum calculation and TCP segmentation
  • Large on chip receive packet buffer (520 KB)
  • Large on chip transmit packet buffer ( 320KB)

LAN Features:

  • IEEE 802.x flow control support
  • IEEE 802.q VLAN tagging support
  • IEEE 802.1p layer 2 priority encoding
  • Jumbo Frame (up to 16KB)
  • Link Aggregation and Load Balancing
  • RFC2819 RMON MIB statistics
  • TCP Segmentation Offload Up to 256KB
  • Ipv6 Support for IP/TCP Receive Checksum Offload
  • DDP Offload
  • LEDs indicator for link/Activity

PE10G2DBI

Dual port Fiber 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

Bypass Specifications:

WDT Interval (Software Programmable): 3,276,800 mSec (3,276.8 Sec): Maximum
100 mSec ( 0.1 Sec) : Minimum
WDT Interval = (2^wdt_interval_parameter)*(0.1) sec.
wdt_interval_parameter: { Valid Range: 0-15}

Short Range Fiber 10 Gigabit Ethernet Technical Specifications- (10GBase-SR)

IEEE Standard / Network topology: Fiber 10Gigabit Ethernet, 10GBASE-SR (850nM LAN PHY)
Data Transfer Rate: 10.3125GBd
Cables and Operating distance:
Up to:
62.5um, 160MHz/Km 13m *
62.5um, (OM1)200MHz/Km 16.5m*
50um, 400MHz/Km 33m *
50um, (OM2)500 MHz/Km 41m *
50um, (OM3)2000MHz/Km 150m*
Defined as half as the distance as specified in the optical transceiver
Optical Transmit Power: Typical: -2.3 dBm
Minimum: -3 dBm
Optical Receive Sensitivity: Typical: -16.8 dBm
Maximum: -11.1 dBm
Maximum Input Power: Maximum: +0.5dBm
Insertion Loss: Bypass Mode:
Insertion loss (Optical Power attenuation between TX to RX)
Typical: 1.0 dB (From RX to TX)
Maximum 1.9 dB

Long Range Fiber 10 Gigabit Ethernet Technical Specifications- (10GBase-LR)

IEEE Standard / Network topology: Fiber 10Gigabit Ethernet, 10GBASE-LR (1310nM LAN PHY)
Data Transfer Rate: 10.3125GBd
Cables and Operating distance:
Up to:
Single Mode Fiber 9u, Maximum length 5 KM*
Defined as half as the distance per the optical transceiver
Optical Transmit Power: Typical: -2.3 dBm
Minimum: -3 dBm
Optical Receive Sensitivity: Typical: -16.8 dBm
Maximum: -11.1 dBm
Maximum Input Power: Maximum: +0.5dBm
Insertion Loss: Bypass Mode:
Insertion loss (Optical Power attenuation between TX to RX)
Typical: 1.0dB (From RX to TX)
Maximum 1.6dB

Operating Systems Support

Operating system support: Linux

General Technical Specifications

Interface Standard: PCI-Express Base Specification Revision 2.0
Board Size: Standard height short add-in card 167.64mm X 106.68mm (6.60”X 4.2”)
PCI Express Card Type: X8 Lane
PCI Express Voltage: +3.3V +-9%,
+12V +- 8%
PCI Connector: X8 Lane
Controller:  Intel 82598EB
Holder: Metal Bracket
Weight: 320g (11.2oz)
Power Consumption: PE10G2DBi-SR
23.8 W, 1.6A at 12V and 1.5A at 3.3V: Typical two ports operate at 10G
23.3W, 1.5A at 12V and 1.4A at 3.3V: Typical No link at all ports
PE10G2DBi-LR
24.2W, 1.6A at 12V and 1.5A at 3.3V: Typical two ports operate at 10Gbit/s.
19.2W, 1.6A at 12V: Typical No link at all ports
4.8W, 1.45A at 3.3V: Typical No link at all ports
Operating Humidity: 0%–90%, non-condensing
Operating Temperature: 0°C – 40°C (32°F – 104°F)
Storage: -20°C–65°C (-4°F–149°F)
EMC Certifications: FCC Part 15, Subpart B Class B
Conducted Emissions
Radiated Emissions
CE EN 55022: 1998 Class B Amendments A1: 2000; A2: 2003
Conducted Emissions
Radiated Emissions
CE EN 55024: 1998 Amendments A1: 2000; A2: 2003
Immunity for ITE Amendment A1: 2001
CE EN 61000-3-2 2000, Class A
Harmonic Current Emissions
CE EN 61000 3-3 1995, Amendment A1: 2001
Voltage Fluctuations and Flicker
CE IEC 6100-4-2: 1995
ESD Air Discharge 8kV. Contact Discharge 4kV.
CE IEC 6100-4-3:1995
Radiated Immunity (80-1000Mhz), 3V/m 80% A.M. by 1kHz
CE IEC 6100-4-4:1995
EFT/B: Immunity to electrical fast transients 1kV Power
Leads, 0.5Kv Signals Leads
CE IEC 6100-4-5:1995
Immunity to conductive surges COM Mode; 2kV,
Dif. Mode 1kV
CE IEC 6100-4-6:1996
Conducted immunity (0.15-80 MHz) 3VRMS 80% A.M.
By 1kHz
CE IEC 6100-4-11:1994
Voltage Dips and Short Interruptions
V reduc >95%, 30% >95% Duration 0.5per, 25per, 250per
MTBF*: 34 (Years)
* The prediction was performed for 40°C Ambient temperature, GB Environmental condition.
The reliability prediction was performed in accordance with Telcordia SR-332

LEDs

LEDs: (2) LEDs per port
Link: Turns on link (yellow).
ACT: Blinks on activity (green).
(1) Bi-Color LED:
Bypass: Green on Bypass, Yellow on Disconnect, off on Normal
LEDs location: LEDs are located on the PCB, visible via holes in the metal bracket holder
Connectors: (2) LC

 

Functional Description

Director Director – Content Aware Bypass

Silicom’s 10 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where rules specify which packets are directed to the host system and which packets are directed to the other port (Bypass).

Figure 1: Content Aware Bypass Functional Block Diagram

DBI1

Figure 1 illustrates functional block diagram of content aware Bypass:

Packets received in port A and meet rule are directed to port B, other packets are directed to port C (Bypass).

Packets received in port C and meet rule are directed to port D, other packets are directed to port A (Bypass).

Director Content Awar TAP
Silicom’s 10 Gigabit Ethernet content aware director Provides intelligent packet redirection capability where all packets are directed to the other port (Bypassed) and rules specify which packets are copied to the host system (TAP).

Figure 2: Content Aware TAP Functional Block Diagram

DBI2

Figure 2 illustrates functional block diagram of content aware TAP:

Packets received in port A and meet rule are directed to ports B and C (TAP), other packets are directed to port C (Bypass).

Packets received in port C and meet rule are directed to ports D and A (TAP), other packets are directed to port A (Bypass).

Director – Content Filtering NIC

Silicom’s 10 Gigabit Ethernet content aware provides intelligent packet redirection capability where rules specify which packets are directed to the host or dropped.

Figure 3: Content Aware Filtering NIC Functional Block Diagram

DBI3

Figure 3 illustrates functional block diagram of content aware TAP:

Packets received in port A and meet rule, direct to port B. Packets received in port A and do not meet rule are dropped.

Packets received in port C and meet rule, direct to port D. Packets received in port C and do not meet rule are dropped.

Bypass / Disconnect

Silicom’s Bypass adapter supports Normal, Bypass and Disconnect modes. In Normal mode, the ports are independent interfaces (see Figure 1: Normal mode, one Bypass pair is illustrated).

Figure 4: Normal Mode Functional Block Diagram

DBI4

In Bypass mode, the connections of the Ethernet network ports are disconnected from the interfaces and switched over to the other port to create a crossed connection loop-back between the Ethernet ports. The connections of the interfaces are left unconnected. (See Figure 2: one Bypass pair illustrated)

Figure 5: Bypass Mode Functional Block Diagram

DBI5

In Disconnect mode, the transmits connections of the interfaces are disconnected from the ports. The switch / router connected to the adapter does not detect link partner (See Figure 3):

Figure 6: Disconnect Mode Functional Block Diagram

DBI6

Silicom’s Bypass server adapter supports software programmable to select Normal, Bypass or Disconnect modes. Silicom’s Bypass adapters supports Disable Bypass, Disable Disconnected capabilities; hence, if those adapters receive Disable Bypass capability / Disable Disconnect commands, the adapter does not Bypass / does not Disconnect its Ethernet ports, The Disable Bypass Capabilities are reserved also after power off. This feature enables to emulate a standard NIC.

PE10G2DBI

Dual port Fiber 10 Gigabit Ethernet PCI Express Content Director Server Adapter Intel® Based

P/N

Description

Notes

PE10G2DBI-SR Dual port Fiber (SR) 10 Gigabit Ethernet PCI Express Content Director Server Adapter RoHS Compliant,
X8, based on Intel 82598
PE10G2DBI-LR Dual port Fiber (LR) 10 Gigabit Ethernet PCI Express Content Director Server Adapter RoHS Compliant,
X8, based on Intel 82598

 

Notes: -SD: Side Driver

1V3